The present invention relates to computer systems and in particular to a system for the verification of correct information transfers between certain of the circuits of the system and surrounding circuits.
FIG. 1 is a partial diagram of a conventional computer system. This system comprises a computer 10 associated to a network 11 to which are connected various elements, especially servers 12. A server generally comprises an interface board 13 between the network 11 and a system bus SB to which are connected input/output boards 14. The input/output boards 14 are, for example, connected to terminals, to a telephone network and/or to peripheral devices.
All of the boards of the server 12 are generally managed by the interface board 13. Each of the server boards comprises a microprocessor managing the board itself and allowing it to achieve various operations, especially testing itself and communicating the test results to the computer system.
FIG. 2 is a simplified schematic diagram of a board 14 which is here an input/output board. This board comprises a microprocessor 20 connected to a system bus D,A,C internal to the board, comprising a data bus D, an address bus A and a control bus C. The data bus comprises, for example, 16 lines for transmitting 16 bit words. The address bus comprises, for example, 24 lines for communicating 24 bit addresses. The control bus comprises at least three lines which are a clock line (CK), a read/write line (R/W), and a data reception acknowledgement line (DTACK). In the following description, it will only be referred to line R/W, the functions of the other lines not being necessary for understanding the invention. Line R/W allows, as will be seen later, the microprocessor to establish a reading mode (R) or a writing mode (W).
Peripheral devices, not shown, are connected to input/output (I/O) circuits 21. Each I/O circuit can manage a plurality of peripheral devices, for example 8. Each I/O circuit comprises an input connected to a chip-select line CS and an output connected to an interrupt request line IRQ. The CS lines are connected to outputs of an address decoder circuit 23 connected to a plurality of the address bus lines, corresponding to high address lines AH. The IRQ lines are connected to inputs of an interrupt priority level decoder circuit 25 which provides the microprocessor 20 with a binary coded priority level through lines IPL, for example three lines.
For normal operation, circuit 23 is only connected to the address bus and circuit 25 is not connected to any bus. But, generally the decoding functions of decoder circuits 23 and 25 are programmable. Therefore, the address decoder circuit 23 is also connected to the data bus and the decoder circuit 25 is connected to low address lines AL, to a chip-select line CS of circuit 23 and to the data bus.
Each of the I/O circuits is also connected to a certain number of the data bus lines, for example 8, for transmitting 8 bit words between the board and the peripheral device, and to low address lines AL.
FIG. 3 is a partial diagram of internal circuitry of an input/output circuit 21. This input/output circuit is intended to communicate with two non-represented peripheral devices. Three registers are associated with each peripheral device, namely a data transmission register TR, a data reception register RR and a control register CR. Each of the registers is also connected to the control bus C, to the data bus D and to an internal chip-select line CSi allowing an internal address decoder 32 to select the register. Address decoder 32 is connected to the CS line of circuit 21 and to at least three low address lines in order to be able to select the six registers. All the inputs and outputs of the circuit are buffered by buffers 33.
Words to be transmitted to the peripheral device are written into register TR; the peripheral device writes words which are to be transferred to the data bus in register RR; and in register CR, is written control information which determines a communication protocol, i.e. how data must be communicated with the peripheral device, such as the communication speed, the number of bits per words, the parity of the words. Registers CR are connected to internal circuitry (not shown) which exploit the data of these registers for managing the communication.
In order to read or write in one of the registers of circuit 21, the following operations are performed:
setting by the microprocessor the R/W line of the control bus to a logic state, for example "1" to read and "0" to write; PA1 issuing by the microprocessor an address on the address bus for selecting the desired register; PA1 decoding the high address AH by the decoder circuit 23 which accordingly selects a circuit 21 by setting the associated CS line to an active state, for example "0"; PA1 decoding the low address AL by decoder 32 of the selected circuit 21, this decoder selecting the desired register through the associated chip-select line CSi, causing the selected register to write its contents on the data bus if the R/W line is at "0", or to read a word supplied by the microprocessor to the data bus if the R/W line is at "1".
When a peripheral device wishes to communicate with the system, the associated circuit 21 forces its output IRQ to an active state, for example "0", which corresponds to an interruption request. The circuitry establishing this interruption request is not described. Decoder circuit 25 converts this request into a priority level IPL as a function of the priority attributed to the concerned circuit 21. According to the priority level, the microprocessor does or does not interrupt operations of the concerned circuit 21. When the microprocessor interrupts operation, the microprocessor searches for the circuit 21 which requested the interruption by sequentially selecting in read mode (line R/W at "1") the registers RR of circuits 21. The register RR of circuit 21 which requested the interruption writes its contents on the data bus when it is selected and output IRQ of the concerned circuit 21 is then reinitialized.
Common failures of a board are due to bad access paths between various circuits of a board. An access path is defined as comprising a conductive track on the board, the soldered connection of the track to a pin of a circuit, the connection of the pin to a buffer of the circuit chip, the connection of the buffer to metallizations of the chip, and eventually connections through various internal circuits of the chip. Defects in the access paths can result, for example, from poor soldering of the pins to their tracks, from destruction of a buffer and/or from poor chip silicon quality.
In order to detect some of these defects, the microprocessor periodically executes, for example during power-on, a board test program. One of the tests involves verifying the communication between the board and peripheral devices. Therefore, communications between the microprocessor and the input/output circuits are generally tested. If this test is successful and if the peripheral device misfunctions, the defect is localized to the communication between the input/output circuit and this peripheral device, or in the peripheral device.
A conventional test involves checking the connection of the input/output circuit to the data bus, this connection being a common failure source. Register RR is generally read-only, i.e. signals cannot be written in to register RR via the data bus. In register CR, some bits are read-only and the writing in the others of inadequate information can result in an undesirable functioning of the peripheral device. Register TR can be read or written from the data bus and it is in the register that test words are written because it happens to be the most convenient. The written words are then read and compared to the test words whereby it can be determined whether the access paths between the register and the data bus are defective.
However, only words corresponding to data which are ignored by the associated peripheral device can be written in register TR because it is undesirable to operate the peripheral device in an uncontrolled manner. Thus, the set of words that can be written in the register is limited and the failure possibilities of all the access paths cannot be exhaustively tested. Moreover, the set of words that can be written in the register depends on the type of peripheral device connected to the register, hence one specific test program per type of peripheral device must be provided.
Testing only the input/output circuits does not always allow a failure to be localized. Indeed, if the test program indicates a failure, this failure can be due to a bad connection to the data bus, and, for example, to a failure of the address decoder circuit not sending a chip-select.
Testing methods for intermediate circuits in order to better localize failures exist. They consist in simulating peripheral device accesses and the actions of the peripheral devices. Therefore, the previously mentioned transmission and reception registers TR, RR, of the input/output circuits are of a special type. They can be put in a test mode during which their connections to the peripheral devices are interrupted and registers TR are connected to the associated registers RR. The words written into register TR are then transferred to associated register RR where they can be read, which allows checking of whether data, even erroneous, effectively reaches register TR and at the same time if this data generates an interrupt request when it reaches register RR.
However, for reliable verification of the intermediate circuits, at least partial correct functioning of the input/output circuits is needed. For example, if all the lines of the data bus arriving at the input/output circuit are interrupted, this circuit also reacts as if it is not selected. In any case, if the input/output circuit does not generate an interrupt request, it will not be known if it is the input/output circuit that is defective or if it is the priority level decoder circuit. Thus, in spite of this test method with special registers TR and RR, in many cases a failure cannot be accurately localized.